1. Technical Field
Embodiments disclosed herein relate generally to a multi-phase clock generating circuit and a method for controlling the same, and more particularly to a multi-phase clock generating circuit capable of improving a phase difference and a method for controlling the same.
2. Related Art
As technologies of memory systems continue to develop, the demand for high-speed data processing increases and high-speed data transmission rate in semiconductor memory devices is required. A prefetch scheme is applied to an internal circuit of a semiconductor memory device to satisfy the high-speed data transmission rate or high-bandwidth of the data which are input serially from an external circuit. In the prefetch the serial data are parallelized by latch circuits. The prefetch is achieved in the semiconductor memory device by using multi-phase clock signals that are out of phase with each other.
Multi-phase clock signals can be generated, for example, by a Phase Locked Loop (PLL) circuit or a Delay Locked Loop (DLL) circuit. However, feedback loop circuits, including the PLL and the DLL, require a large area and consume a large current, and as such, feedback loop circuits are not suitable for a low-power operating circuit. As an alternative, phase interpolators are widely used to generate clock signals based on the phase-difference interpolation, using two clock signals supplied from an external circuit.
In more detail, the phase interpolators generate new clock signals, each of which has a center phase between the two input clock signals from the external circuit. However, as the frequency of the clock signal increases, positioning the center phase exactly at the center between the two input clock signals becomes increasingly difficult, and therefore, problematic. Accordingly, as the frequency of the clock signal increases, a phase offset can be caused every clock signal of the multi-phase resulting in an error in the phase. Furthermore, when the data are transmitted in synchronization with the multi-phase clock signal, the actual valid window of the data is reduced. Therefore, a circuit for generating multi-phase clock signals with reduced current consumption and without an error is needed.